Integrated circuits are often organized in repetitious dies that are arranged on the face of a semiconductor layer. Die-to-die signal transmission lines are used to link the dies together. The simplest sort of die-to-die signal transmission line consists of an CMOS inverter in the first die, a transmission line connected between an output of the first inverter and the input of a second inverter in the second die, and an output from the second inverter.
As system complexity and the I/O count of dies increased, more sophisticated signal transmission circuits became necessary since the power dissipation of the simple inverter design began to account for a non-negligible part of the total system power dissipation. Further, die-to-die signal transmission delays began to limit the system performance.
To improve the performance of die-to-die transmission lines, more complex circuits have been fashioned. Examples are described in H. Bakoglu and J. Meindle, "New CMOS Driver and Receiver Circuits Reduce Interconnection Propagation Delay," Proceedings of the 1985 Symposium on VLSI Technology. In one of these circuits, a half V.sub.dd is employed instead of a ground or a V.sub.dd precharge in a signal transmission line to improve the signal delay and power dissipation of the transmission line. A disadvantage of this particular circuit is that a DC current flows during the precharge at the receiver end, thereby dissipating power. Another circuit proposed in the above paper requires many more control transistors and still does not completely avoid the dissipation of DC power. Moreover, it is difficult to achieve a stable V.sub.dd -to-precharge with this last circuit. The unstable precharge level creates the possibility of a system malfunction due to incorrect signal transfer.
In view of the foregoing, a need has arisen for a signal transmission circuit with a simple dynamic precharge circuit, a non-full voltage swing and a simple dynamic sensing circuit.